SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.
When you build a CPU in FPGA, you generally have to make one of three choices. You can roll your own, which is great fun but requires a lot of work both on the design and the associated tools, for example, a cross-compiler or operating system. You can “borrow” an existing architecture or design which may or may not be legal, depending on what you pick. You can also use a commercial offering. While some of these are free in some circumstances, you’ll pay for anything substantial.
This open implementation offers you an easy way to leverage some great tools. There’s a debugging interface for GDB and a FreeRTOS port. You have a 32-bit part that can achieve 1.16 Dhrystone MIPS/MHz even with all features turned on. This is comparable to commercial 32-bit processors.
The documentation is good, too. You can simulate the CPU on a Linux system. There are implementation numbers for some common FPGAs, too. For example, a Cyclone V chip can support 115 MHz to 187 MHz, depending on options. Even a Cyclone II can run a bare-bones version at 156 MHz or a tricked out version at 92 MHz.
There’s even a complete system on chip design included as an example. Honestly, embarking on such a custom project wouldn’t be a half-hour project. But with the documentation provided, you could either learn a lot or get a great head start on fielding a substantial processor in an FPGA. There’s even an example of adding a completely new instruction module.
We’ve talked before about the difficulties in bootstrapping an entirely new CPU. With VexRiscv, you don’t have to worry about that. Of course, if you want to do everything yourself, here’s some inspiration.