The 500,000 sample per second rate and the 1024 sample buffer isn’t going to put any logic analyzer vendors out of business, but it is still enough to help you figure out why that SPI or I2C logic is messed up. It looks like a fun project that could have some usefulness.
[Juan] provides all the design files in his post. He also notes that he had to reduce the speed on the CPU to accommodate the LCD. He has the CPU running at 5 V because the 5 V part has a higher frequency rating and he hopes to get the speed to 40 MHz which would, presumably, increase the sampling rate for the logic analyzer.
If you want something more serious, an FPGA is the way to go. Even a cheap FPGA board can easily do many more channels at 96 million samples per second. Then again, unlike Digitool, you’ll need a PC to display the results.
Filed under: Microcontrollers